CVE-2025-0647

HIGH

7.9

Description

In certain Arm CPUs, a CPP RCTX instruction executed on one Processing Element (PE) may inhibit TLB invalidation when a TLBI is issued to the PE, either by the same PE or another PE in the shareability domain. In this case, the PE may retain stale TLB entries which should have been invalidated by the TLBI.

Details CVE

Score CVSS v3.17.9

SeveriteHIGH

Vecteur CVSSCVSS:3.1/AV:L/AC:L/PR:H/UI:N/S:C/C:H/I:H/A:N

Vecteur d'attaqueLOCAL

ComplexiteLOW

Privileges requisHIGH

Interaction utilisateurNONE

Publie1/14/2026

Derniere modification1/26/2026

Sourcenvd

Observations honeypot0

Produits affectes

arm:c1-premiumarm:c1-premium_firmwarearm:c1-ultraarm:c1-ultra_firmwarearm:cortex-a710arm:cortex-a710_firmwarearm:cortex-x2arm:cortex-x2_firmwarearm:cortex-x3arm:cortex-x3_firmwarearm:cortex-x4arm:cortex-x4_firmwarearm:cortex-x925arm:cortex-x925_firmwarearm:neoverse-n2arm:neoverse-n2_firmwarearm:neoverse-v2arm:neoverse-v2_firmwarearm:neoverse-v3arm:neoverse-v3_firmwarearm:neoverse-v3aearm:neoverse-v3ae_firmware

Faiblesses (CWE)

CWE-226

References

https://developer.arm.com/documentation/111546(arm-security@arm.com)

https://graph.volerion.com/view?ID=CVE-2025-0647(134c704f-9b21-4f2e-91b3-4a467353bcc0)

Correlations IOC

Aucune correlation enregistree

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